Senior Principal ASIC FPGA Engineer
$191,146–$191,146 year
HybridBoise, Idaho, United States
Job Summary
Own the architecture and drive RTL design for ASIC/FPGA systems, defining microarchitecture, bus fabric integrity, and interface specifications from concept through silicon. Navigate synthesis, place and route, and static timing analysis to close timing at advanced nodes, fixing root causes rather than just running tools. Lead verification by developing test plans, driving closure on failures, and serving as the primary point of contact for functional criteria. Manage JIRA triage, conduct code reviews, and support program planning through Integrated Master Schedule development and earned value reporting. Guide technology selection for foundries and EDA tooling, while mentoring engineers and collaborating across multi-divisional product teams.
Required Qualifications
- Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field
- Minimum of 10 years of relevant experience
- Master's degree
- Minimum of 8 years of relevant experience
- Department of Defense Secret security clearance
- U.S. Government security investigation eligibility
- Eligibility requirements for access to classified information
- U.S. citizenship
- 10–15+ years of ASIC/FPGA design experience
- Majority of experience spent as an RTL designer
- Proven experience taking designs through full ASIC tape-out
- Deep familiarity with FinFET process nodes (7nm, 5nm, or similar)
- Experience with commercial foundry flows (TSMC, GlobalFoundries, Samsung, or equivalent)
- Expert-level understanding of ASIC/FPGA engineering concepts
- Expert-level understanding of RTL coding practices
- Expert-level understanding of synthesis flows
- Strong familiarity with industry-standard EDA tools (synthesis, simulation, formal verification, STA)
- Demonstrated ability to operate independently
- Proficiency in JIRA for issue tracking and backlog management
- Proficiency in Microsoft Office for documentation and communication
Desired Qualifications
- Understanding the nuances of FinFET vs. planar technology
- Experience with RTL design and microarchitecture definition
- Bus fabric design and correctness verification
- Clock domain crossing (CDC) analysis and closure
- Reset sequencing and order-of-operations validation
- Timing closure at advanced nodes — not just constraint writing, but root cause analysis and fixing
- Power analysis and optimization
- Track record of innovative technical contributions
- Solid understanding of organizational processes and the ability to apply them pragmatically across a program lifecycle, including schedule management and earned value inputs
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