Senior Principal Analog Lead – HBM PHY

Senior Principal Analog Lead for HBM PHY responsible for driving the analog/mixed-signal architecture of HBM PHY, including TX/RX design, clocking, DLL/PLL, calibration/margining support, and integration with IO blocks, SI/PI budgets, and system-level modeling. Leads design of high-speed blocks (IO drivers/receivers, equalization, clock distribution, timing circuits), collaborates with RTL/logic, physical design, packaging, and system teams, and guides post-silicon bring-up and interoperability with memory vendors. Requires extensive experience in analog/mixed-signal IC design for high-speed interfaces, memory PHYs (HBM/SerDes), and cross-functional leadership across advanced nodes; familiarity with training flows, calibration algorithms, and 2.5D/3D packaging, with a track record of silicon-delivered PHYs and strong emphasis on SI/PI, jitter, and power integrity.