Senior Principal AI Interconnect Architect

Senior Principal AI Interconnect Architect responsible for defining and engineering high-speed networking and communication systems for AI inference infrastructure, including servers, racks, and chips. Design chip-to-chip interconnects and switched fabrics for AI/ML scale-out with focus on bandwidth, latency, power efficiency, scalability, and optimized transport protocols. Consider interconnect technologies such as PCIe, CXL, co-packaged optics, UALink, Ultra Ethernet, and be able to specify scale-out architectures for optimizing power, cost, and performance. Collaborate with SoC, package design, and software teams for seamless integration; participate in industry standard bodies to influence specifications. Familiarity with fabric topologies (Fat tree, Leaf-Spine/Clos, Torus, Meshed) and with GPU/accelerator clusters, data center infrastructure, and various interconnect protocols (PCIe, CXL, NVLink, UALink, Ethernet, Ultra-Ethernet, serial links). Strong modeling and simulation capability to develop performance models. Must have 10-15 years of experience in interconnect technologies and related domains. The role emphasizes architecture, performance optimization, standards participation, and cross-functional collaboration.