Senior Physical Design Engineer

Drive physical implementation of next-generation IPs for AMD Microprocessors, Servers, PCs, and Graphics Cards, focusing on Synthesis, floorplan, placement, clock tree synthesis, routing, and STA closure for high-speed (>2G) designs with complex I/O clocking. Manage implementation activities across PCIe, UCIe, UALink, and Infinity Fabric protocols to achieve best PPA while shortening development schedules. Develop reference floorplans and implementation scripts for SoCs worldwide, collaborating with diverse RTL design and NBIO IP teams. Requires experience in Synthesis, floor-planning, placement, clock trees, post-route timing closure, STA, and scripting in TCL or Python.