Senior Mixed Signal Verification Engineer
On-site · Catania, Sicily, Italy
Job Summary
Senior Mixed Signal Verification Engineer to lead verification strategy for mixed-signal SOC designs at NXP Italy. Responsibilities include developing verification plans, creating functional models of analog blocks using SystemVerilog, developing AMS models for analog blocks, running simulations, tracking coverage of verification plans, ensuring high-quality tape-outs and post-silicon support to resolve silicon issues, and collaborating closely with designers and systems engineers. Required skills include SystemVerilog modeling, analog/digital verification awareness, and strong communication and teamwork. Masters degree is preferred; 5+ years of production mixed signal verification experience is expected.
Required Qualifications
- Bachelor's Degree in Electronic Engineering
- 5+ years of production mixed signal verification
- SystemVerilog modeling experience
- Assertion and checkers experience desired
- Strong communication and teamwork skills
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