Senior Mixed Signal Validation and Debug Engineer

Senior Mixed Signal Validation and Debug Engineer in Intel's HIPD within the Central Engineering Organization. The role focuses on pre-silicon to post-silicon IP design characterizations, test planning with AI-driven tools and pythonSV scripting, SOC board design reviews, and signal/power integrity simulations followed by post-silicon debugging. Responsibilities include identifying and debugging IP-related silicon issues, reproducing issues, performing root-cause analysis and failure analysis, and providing hands-on IP enabling support. The candidate will engage with SOC customers and IP design teams, participate in SOC Power Ons for test chips/products, and lead IP debug activities as needed. Required qualifications include a BS/MS/PhD in a related engineering field, 6+ years of post-silicon validation and debugging experience with serial or parallel IOs, proficiency with lab hardware/software (oscilloscopes, logic analyzers, protocol analyzers, BERTs), and familiarity with DDR/LPDDR/PCIe/USB/Type-C/Die2Die/Ethernet specifications; PHY or Controller experience is acceptable. Desirable skills include IP debug leadership, and knowledge of signal integrity and power delivery; pre-silicon design or simulation experience in logic, circuits, firmware, or MRC is a plus. The role requires on-site presence in Bangalore, India.