Senior Mask Design Engineer - Hardware
HybridTaipei, Taiwan, Taiwan or Hsinchu, Taiwan, Taiwan
Job Summary
Perform physical layout for mixed-signal functions including top level, high speed datapaths, and high-speed clocking designs in sub-micron CMOS technologies using Cadence tools. Collaborate with mixed-signal design engineers to customize layouts for VLSI product integration, covering floor planning, custom layout, and verification against design rules and schematics. Execute DRC and LVS checking flows while customizing decks, leveraging deep FinFET technology expertise and authority with Virtuoso. Work independently on creating high-quality layouts, iterating quickly based on feedback, and utilize scripting languages like Python or Skill as applicable. Join a diverse team driving chiplet interface projects to amplify human creativity and intelligence through NVIDIA's AI infrastructure.
Required Qualifications
- BSEE or equivalent experience
- Minimum of 5+ years industry experience in Mask and Layout Design
- Deep understanding and previous experience for FinFET technology
- Authority with Cadence custom circuit design tools - particularly virtuoso
- Ability to handle fast-paced project and iterate quickly based on designer's feedback
- Ability to work effectively in a team
- Good interpersonal skills
- Enthusiasm
- Positive energy
- Knowledge of DRC and LVS checking flows
- Ability to customize decks
Desired Qualifications
- Scripting languages like perl, python, skill
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