Senior Logic Design Engineer, Cache Coherent Interconnects
$136,000–$264,500 year
Hybrid · Santa Clara, California, United States
Job Summary
As a Senior Logic Design Engineer, you will design CPU on-chip and off-chip interconnect networks, focusing on micro-architectural definition, RTL coding, logic debug, synthesis, and timing closure. Responsibilities include writing high-performance, low-power RTL, collaborating with verification teams, and assisting with timing closure of super units. A Master's Degree and 5+ years of relevant experience are required, along with Verilog expertise and a comprehensive understanding of ASIC design flow.
Required Qualifications
- Master’s Degree in Electrical Engineering, Computer Engineering or Computer Science or equivalent experience
- 5+ years of experience in processor or related high performance semiconductor designs
- Verilog expertise
- Deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug
- Strong background in computer architecture, cache coherency or high speed interconnects
Desired Qualifications
- Strong communication and interpersonal skills
- Mentoring junior engineers and interns
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