Senior Lab Validation Engineer
$160,000–$195,000 year
On-site · San Jose, California, United States
Job Summary
Hands-on lab validation to root-cause customer quality concerns related to high-speed PCIe retimers and SerDes; modify device firmware to test theories, develop corrective actions, and production screens; investigate failures (link training, lane margining, eye closure, jitter, protocol errors, interoperability); debug retimer issues (equalization, pass-through, clocking, bring-up) and PCIe switches (lane bifurcation, hot-plug, multi-port stability); characterize and isolate failures with advanced lab instrumentation (BERT, high-bandwidth scopes, protocol analyzers, VNAs, TDR, spectrum analyzers); design and run stress tests and margining experiments; provide system-level feedback on board layout and firmware interactions; drive physical failure analysis (probing, de-processing, FIB, thermal/voltage stress); document findings and contribute to FA methodologies; collaborate on new product development and evaluation hardware; in-person role based in San Jose, CA; base salary range $160k-$195k.
Required Qualifications
- Bachelor's in Electrical Engineering (minimum)
- 5+ years hands-on high-speed lab experience with protocol analyzers, BERT, real-time scopes, sampling scopes, TDR, and VNA
- Python programming
- Deep understanding of PCIe protocol (Gen6) and SerDes signal integrity
- Hands-on experience debugging retimers (equalization tuning, clocking, reset/link sequencing)
- Hands-on experience debugging PCIe switches (lane bifurcation, hot-plug, multi-port link stability, compliance failures)
- Strong NRZ/PAM4 background with jitter, CDR/PLL, equalization (DFE, CTLE, FFE) and power integrity
- Experience in post-silicon validation and bring-up of high-speed PHYs or retimers
- Strong problem-solving and communication skills
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