Senior IP Design Engineer
On-siteЖана-Аул, Respublika Altay, Russian Federation
EXPIREDЖана-Аул, Respublika Altay, Russian FederationOn-siteContractSenior LevelSmall
ContractSenior LevelSmall
Job Summary
Design high-performance IP targeting FPGA/Adaptive SoC technology using SystemVerilog RTL. Deliver synthesis-ready designs meeting timing and integration requirements. Apply deep understanding of FPGA/Adaptive SoC design flow including P& R and timing closure. Leverage expertise in Vivado/Vitis, Python/Tcl scripting, and Git/CI/CD for 100Gb Ethernet, PCIe Gen5, and AMBA/AXI implementations. This six-month FTE role in Romania requires immediate start. Manning Global represents the client for this search.
Required Qualifications
- SystemVerilog RTL design
- 100Gb Ethernet
- PCIe Gen5
- AMBA/AXI
- Deep understanding of FPGA/Adaptive SoC design flow including P& R and timing closure
- Vivado/Vitis expertise
- Python/Tcl scripting
- Git & CI/CD experience
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