Senior IC Packaging Engineer
On-site · Ho Chi Minh City, Ho Chi Minh City (HCMC), Vietnam
Job Summary
Senior IC Packaging Engineer to provide technical leadership and architectural ownership of advanced IC and System-in-Package (SiP) packaging. Lead chiplet-based packaging strategies (including UCIe), define substrate stack-ups, materials, and BGA/SiP architectures, drive SF/PI/thermomechanical trade-offs, and engage OSATs/foundries for manufacturing readiness. Role includes hands-on package design and layout, collaboration across cross-functional teams, and shaping long-term packaging strategy for high-performance, low-power packaging across 2D and 2.5D architectures, including PCIe, CXL, LPDDR5, and other multi-gigabit interfaces.
Required Qualifications
- BSEE or MSEE in Electrical Engineering (PhD a plus)
- Minimum of 10+ years of IC packaging experience
- Deep hands-on expertise in Flip-Chip BGA (FCBGA) and System-in-Package (SiP)
- RDL, silicon interposers, and chiplet architectures (UCIe)
- Strong understanding of electrical, mechanical, thermal, and reliability design trade-offs
- DFM and yield optimization
- Experience with high-speed SerDes packaging (PCIe Gen5, LPDDR5/LPDDR5X)
- Collaboration with OSATs, foundries, and substrate suppliers
- Technical leadership of packaging programs
- Cross-functional leadership across design, product, test, operations, reliability, and customer teams
- Cadence Allegro APD or equivalent EDA tools
- S-parameter extraction and PDN optimization using HFSS, SIwave, or Ansys Designer
Apply with one swipe on Sorce. We auto-fill applications and apply on your behalf — no cover letters, no 40-minute forms.
Hiring someone like this?
Get your role in front of qualified candidates on Sorce.