Senior IC Packaging Engineer
On-site · Taipei, Taiwan, Taiwan
Job Summary
Senior IC Packaging Engineer to provide technical leadership and architectural ownership of advanced IC and System-in-Package packaging in a startup environment. Define and drive high-performance, low-power packaging architectures (2D and 2.5D fan-out, chiplet-based designs, UCIe), lead chiplet-based packaging strategies, perform hands-on package design and layout for high-speed interfaces (PCIe, CXL, SerDes), define substrate stack-ups and DFM guidelines, drive SI/PI, thermal, mechanical, and reliability trade-offs, and lead external engagements with OSATs and foundries. Influence product roadmap and manufacturing readiness; establish scalable design methodologies and reusable packaging flows. BSEE or MSEE required; 10+ years of IC packaging experience; deep expertise in FCBGA and SiP, UCIe, RDL, and chiplet architectures; strong cross-functional leadership and autonomous execution.
Required Qualifications
- BSEE or MSEE in Electrical Engineering
- Minimum 10+ years of IC packaging experience
- Deep hands-on expertise in Flip-Chip BGA (FCBGA) and System-in-Package (SiP)
- Experience with RDL, silicon interposers, and chiplet architectures (UCIe)
- Strong understanding of electrical, mechanical, thermal, and reliability design trade-offs
- Experience with high-speed SerDes/PCIe, LPDDR5, UCIe interfaces
- Ability to lead external engagement with OSATs, foundries, and suppliers
- Technical leadership of multiple end-to-end packaging programs
- Experience with cost, yield, schedule, and risk trade-offs at product/portfolio level
- Cadence Allegro Package Designer (APD) or equivalent EDA tools
- Experience building new packaging methodologies or platforms from scratch
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