Senior IC Layout Designer (Remote – USA)
$135,200–$166,400 year
RemoteUnited States
Job Summary
Develop block-level and full-chip physical layouts for complex digital and mixed-signal IC designs, translating schematics into high-quality implementations while maintaining design intent. Perform floorplanning, placement, routing, optimization, and refinement to drive DRC, LVS, and ERC closure, analyzing layouts for parasitics, signal integrity, and timing impact. Collaborate with IC designers, verification engineers, and foundry partners during tapeout and silicon release activities to support improvements in layout methodologies and automation. Mentor junior engineers and contribute technical expertise across the team.
Required Qualifications
- 7+ years of hands-on IC layout design experience in advanced semiconductor technologies
- Strong expertise with industry-standard EDA tools such as Cadence Virtuoso, Synopsys tools, or equivalent platforms
- Deep understanding of CMOS process technology, physical design concepts, and layout best practices
- Proven experience achieving DRC/LVS closure and resolving complex physical verification challenges
- Strong knowledge of parasitic extraction, signal integrity, timing impact, and layout optimization techniques
- Experience collaborating within cross-functional semiconductor design teams
- US Citizen or Lawful Permanent Resident
- 100% Remote (Anywhere in the USA)
Desired Qualifications
- Hands-on experience with FinFET and sub-7nm technology nodes
- Experience with high-speed digital, mixed-signal, or advanced SoC designs
- Familiarity with layout automation and scripting using SKILL, Python, TCL, or similar languages
- Track record supporting successful production tapeouts
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