Senior Hardware Compute Architect (f/m/d)
On-siteAachen, North Rhine-Westphalia, Germany
Job Summary
Define the hardware architecture of a hybrid compute engine, including execution units, memory hierarchy, and interfaces for electronic-photonic cooperation. Architect the system data fabric and interconnect infrastructure using technologies such as UCIe, CXL, and NVLink-class fabrics. Partner with software and photonics teams to define hardware/software interfaces and workload mapping strategies. Evaluate architectural options through quantitative modeling of performance, power, area, and scalability trade-offs. Collaborate with circuit design, RTL, and packaging teams to translate compute primitives into implementable system-level architectures. Own the hardware architecture specification through sign-off, ensuring alignment between system requirements and downstream implementation. This role bridges compute architecture, heterogeneous system design, and electronic-photonic co-design within a team driven by human-centered innovation.
Required Qualifications
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent experience
- 5+ years of experience designing compute hardware architecture at the SoC or system level, ideally involving heterogeneous computing, accelerators, or specialized compute architectures
- Deep expertise in compute architecture, including execution units (scalar, vector, tensor/matrix), workload mapping, memory hierarchy, and system-level architecture trade-offs
- Strong experience architecting high-performance interconnects, data fabrics, and heterogeneous compute systems, including technologies such as UCIe, CXL, UALink, NVLink-class, or comparable architectures
- Experience with architectural modeling and quantitative analysis of performance, power, area, and system scalability to guide hardware architecture decisions
- Proven ability to collaborate across hardware and software teams to define interfaces, requirements, and system-level design decisions
- Experience with architecture modeling and simulation tools, interconnect protocols, and system design workflows, including performance/power modeling environments, CXL, UALink, NVLink-class fabrics, UCIe, Python, C++, SystemC, and architecture specification tools used to develop implementable designs for RTL, physical design, and packaging teams
Desired Qualifications
- Familiarity with photonic or optical compute concepts and their integration with electronic compute architectures will be considered a plus
- Experience with heterogeneous compute architectures involving GPUs, DPUs, FPGAs, custom accelerators, or AI accelerator platforms will be considered a plus
- Experience contributing to industry interconnect standards such as CXL Consortium, UALink, or UCIe Consortium will be considered a plus
Hiring someone like this?
Get your role in front of qualified candidates on Sorce.