Senior Full Chip Physical Design Integration Lead
$164,470–$311,890 year
Hybrid · Hillsboro, Oregon, United States or Beaver Brook, Massachusetts, United States
Job Summary
Senior Chip Physical Design Integration Lead responsible for SOC floorplanning, placement and macro placement optimization, and physical design implementation across the RTL-to-GDS flow for custom IP and SoC designs. Drive optimization across power domains, perform verification and signoff activities (formal equivalence, reliability, power integrity, layout verification) using industry-standard EDA tools, and contribute to methodologies and flow automation. Collaborate with cross-functional teams to ensure product-level parameters and manufacturing readiness.
Required Qualifications
- Bachelor's degree with 8+ years or master’s degree with 6+ years or PhD in Electrical/Electronic Engineering, Computer Engineering, Computer Science or related technical discipline
- 4+ years of experience with physical design flows, including synthesis, place and route, clock tree synthesis, and static timing analysis
- Expertise in design optimization for physical design, multi-power plane design (MPP/UPF), and RTL to GDS workflows
- Hands-on experience with scripting to automate design flows
- Knowledge of EDA tools and methodologies for verification, reliability, timing closure, and power integrity analysis
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