Senior FPGA / RTL Design Engineer - Signal Processing
$125,000–$195,000 year
Hybrid · Irvine, California, United States
Job Summary
Senior FPGA/RTL Design Engineer responsible for efficient implementation of novel signal-processing algorithms for Silvus' MIMO wireless networking products; involve RTL coding, FPGA synthesis, timing closure, hardware verification, and collaboration with RF and Software Engineering teams. Requires strong background in fixed-point DSP designs, clock-domain handling, Xilinx FPGA/SoC experience, and proficiency with Vivado; role includes design architecting, digital design, and test bench development in a hybrid onsite/remote environment.
Required Qualifications
- Bachelor of Science in Electrical Engineering, Computer Science, or related fields
- Minimum 6 years of FPGA design experience; 4 years with a Master of Science; 2 years with a PhD
- Demonstrated experience with fixed-point binary arithmetic and digital signal processing designs
- Proven experience with multiple clock-domain high-utilization FPGA designs
- Experience with Xilinx FPGAs, SoCs, and the Vivado IDE
- Must be a U.S. Citizen due to clients under U.S. government contracts
- All employment is contingent upon the successful clearance of a background check
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