Senior FPGA Engineer

Senior FPGA Engineer responsible for designing, implementing, and optimizing a massively parallel, ultra-low-latency FPGA pipeline across a fleet of FPGAs; build and optimize real-time ML inference pipelines on FPGA fabric; collaborate with software, electrical, and process engineering to advance system-level FPGA capabilities; develop RTL components and IP blocks with strict timing, resource, and latency requirements while enabling high-performance signal processing for a distributed compute platform that interfaces with high-power laser systems. The role emphasizes hands-on RTL/HDL design, timing closure, and integration within cutting-edge heterogeneous hardware, with a strong focus on deterministic latency and scalable architectures and requires full-time onsite work at the Hawthorne, CA location.