Senior Engineer (Level 2)-Physical Design

Senior Engineer (Level 2) for Physical Design focused on floor-planning, timing constraints, and RTL-to-GDSII flows. Responsibilities include block-level place-and-route, physical synthesis, clock tree optimization, routing, extraction, timing closure across corners; capable of performing ECOs independently; collaborating with design teams to close CTS, IO timing, and DFT timing; driving digital design automation, flow automation, and regression from RTL to GDSII for complex SoCs. Requires 4-year degree with at least 5 years of related experience (or advanced degree with experience) and willingness to work in Noida, India. Location: Noida, India (World Trade Tower, eInfochips).