Senior Engineer (Level 2)
On-site · Bengaluru, Karnataka, India
Job Summary
Senior Engineer (Level 2) focusing on SOC/IP/block level functional verification with SystemVerilog/UVM. Requires 4–8 years of experience, strong UVM/SystemVerilog skills, development of testplans and testbenches, verification environment components, interface agents and Scoreboard, plus experience delivering 1–2 SoC/IP verification projects. Knowledge of Ethernet, PCIe, MIPI, USB, AMBA or similar protocols, debugging RTL/testbench issues, achieving verification closure through coverage and bug reports, and scripting maintenance. Based in Bangalore, India (IN).
Required Qualifications
- 4 to 8 years of experience in SOC/IP/block level functional verification using SystemVerilog/UVM
- Strong knowledge of UVM, advance UVM,System Verilog
- Must have worked on development of testplan, testbench components, verification environment, interface agents, Scoreboard in UVM
- Must have executed at-least 1 to 2 SoC/IP Verification projects.
- Knowledge of at least one industry standard protocols like Ethernet, PCIe, MIPI, USB, AMBA or similar is required.
- Skills to debug RTL & testbench issues, test failures.
- Experience on verification closure by closing Coverage and bug reports
- Primarily knowledge of Script development and maintenance
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