Senior Engineer (Level 2)

Senior Engineer (Level 2) responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, signal integrity, physical verification and DFM. Execute block level place and route assignments from Netlist through GDS flow. Perform full chip implementation of complex SoCs (RTL-to-GDSII) if needed. Close STA timing across all corners and modes for blocks and should be able to generate ECO independently. Work with design teams for closing CTS, IO timing, DFT timing. Responsible for digital design automation, flow-automation and regression across RTL-to-GDSII.