Senior Engineer (Level 2)
On-site · Noida, Uttar Pradesh, India
Noida, Uttar Pradesh, IndiaOn-siteFull TimeSenior LevelNot SpecifiedUnknown
Type
Full Time
Level
Senior Level
Education
Not Specified
Company size
Unknown
Job Summary
Senior Engineer (Level 2) responsible for SystemVerilog/UVM-based functional verification of SOCs/IPs, including development of testplans and testbenches, verification environment components, interface agents and scoreboards; ability to debug RTL and testbench issues, drive verification closure through coverage and bug reports, and apply scripting skills; requires 4-8 years of experience with industry-standard protocols (Ethernet, PCIe, MIPI, USB, AMBA). Located in Noida, India.
Required Qualifications
- 4 to 8 years of experience in SOC/IP/block level functional verification using System Verilog/UVM
- Strong knowledge of UVM, advanced UVM,System Verilog
- Experience in development of testplan, testbench components, verification environment, interface agents, Scoreboard in UVM
- At least 1-2 SoC/IP verification projects completed
- Knowledge of industry standard protocols such as Ethernet, PCIe, MIPI, USB, AMBA or similar
- Skills to debug RTL & testbench issues, test failures
- Experience on verification closure by closing Coverage and bug reports
- Script development and maintenance
- Understanding of customer dynamic environment changes and ability to adapt run time changes
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