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Maxim IntegratedPosted 1 month ago

Senior Engineer, Digital Design Engineering

On-siteCork, Munster, Ireland or Catania, Sicily, Italy

Full TimeSenior LevelMasters DegreeLarge

Job Summary

Conduct FPGA prototyping and develop models with self-checking mechanisms for FPGA hardware and software codesign. Perform Verilog/SystemVerilog RTL design, architectural specification of blocks, and IP block integration while interacting with verification, analog, and implementation teams. Execute static timing analysis, define timing constraints, and ensure designs meet area, low-power, manufacturing test, and timing targets. Collaborate with product development teams to align digital system architecture with the product roadmap and verify blocks using UVM.

Required Qualifications

  • Bachelor's or Master's degree, in Engineering (Electronic Engineering) or equivalent
  • Architectural design and specification of complex systems, especially in system on chip with processors
  • Deep knowledge of FPGA development flow
  • FPGA modelling
  • Verilog/SystemVerilog RTL design - with emphasis on AHB, AXI protocols and processor architecture on ARM cores
  • Design to meet timing, area, low-power, manufacturing test and timing targets for market
  • Ability to work well in a diverse team environment
  • Strong interpersonal, teamwork and communication skills
  • Precise documentation and attention to detail
  • Quick to adopt new technologies
  • Be self-motivated and enthusiastic
  • Good problem solving skills
  • Architected design and specification of blocks and platforms
  • Act as design hub to interact with stakeholders – test, application, physical implementation, verification
  • Design to meet area, low-power, manufacturing test and timing targets
  • Intellectual Property (IP) block design and integration
  • Perform timing, power and CDC analysis on design
  • Verification of blocks using UVM
  • Mixed-signal integration and verification / co-simulation
  • Working with product development teams to align digital system architecture and methodologies with product roadmap
  • Required Travel: Yes, 10% of the time
  • 1st Shift/Days

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