Senior Digital IC Verification Consultant
On-siteHerlev, Region Hovedstaden, Kingdom of Denmark
Herlev, Region Hovedstaden, Kingdom of DenmarkOn-siteContractSenior LevelSmall
ContractSenior LevelSmall
Job Summary
Conduct metric-driven functional and code coverage closure for digital IC verification projects using Synopsys VCS and VC Formal. Implement SystemVerilog testbenches, SV assertions, and coverage models while debugging issues with Verdi. Manage version control via Git and execute test implementation in TCL, Python, and SystemC. Execute hierarchical verification plans to ensure coverage closure targets are met. This 12-month onsite role begins May 1st and focuses on delivering rigorous verification solutions for complex digital IC designs.
Required Qualifications
- Verilog
- System Verilog
- Python
- SystemC
- TCL
- Makefiles
- Metric driven functional verification
- functional coverage closure
- code coverage closure
- SV assertion
- SystemVerilog Testbench implementation
- Test implementation in TCL
- Coverage model implementation
- Reference model implementation
Desired Qualifications
- UVM
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