Senior Digital Design Engineer, HBM
On-siteRichardson, Texas, United States
Job Summary
Drive all stages of the digital design flow, including concept definition, RTL implementation, and post-silicon debug. Develop high-quality RTL in Verilog/SystemVerilog using scalable techniques and define micro-architecture for logic blocks like FSMs and datapaths. Analyze tradeoffs across area, power, and latency while utilizing AI-enabled tools for daily execution. Perform CDC/RDC analysis, apply clocking strategies, and support synthesis and static timing analysis by debugging SDC constraints. Collaborate with verification, DFT, and physical design teams to ensure robust design closure and high coverage.
Required Qualifications
- Drive all stages of the digital design flow, including concept definition, specification, RTL implementation, verification support, documentation, and post-silicon debug
- Develop high-quality RTL in Verilog/SystemVerilog using scalable, parameterized design techniques aligned to architectural specifications
- Define and refine micro-architecture for digital logic blocks, including FSMs, datapaths, FIFOs, pipelines, and arbitration logic
- Analyze tradeoffs across area, power, latency, and throughput, providing clear documentation and communication of design decisions
- Utilize AI-Enabled tools to assist with every day execution
- Perform CDC/RDC analysis, apply sound clocking and reset strategies, and identify early timing challenges
- Support synthesis and static timing analysis by creating and debugging SDC constraints, and interpreting timing reports
- Apply low-power design methodologies including CPF/UPF, clock gating, multi-domain partitioning, and isolation/level shifter strategies
- Collaborate with verification, DFT, physical design, and CAD teams to ensure robust design closure and high coverage, including scan/ATPG readiness and functional/formal verification support
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