Senior Digital ASIC Design Engineer
$100,000–$140,000 year
Remote · Seattle, Washington, United States or New York City, New York, United States
Seattle, Washington, United States or New York City, New York, United StatesRemoteFull Time$100,000–$140,000 yearSenior LevelMasters DegreeUnknown
Type
Full Time
Level
Senior Level
Education
Masters Degree
Company size
Unknown
Job Summary
Join a pioneering team focused on architecting and optimizing low-power digital logic designs for wireless integrated circuits. Seeking a Senior Digital ASIC Design Engineer with extensive experience in digital ASIC design, ASIC workflow leadership, and multi-clock domain verification. Competitive salary range of $100k - $140k with a comprehensive benefits package and a hybrid work schedule, available immediately.
Required Qualifications
- M.S. in Electrical Engineering/Computer Engineering
- 5+ years digital ASIC design
- Experience with FPGA based prototyping, testing and verification
- Experience working in multi-clock domain systems
- Unit- and system-level verification test design and implementation
Desired Qualifications
- Expertise with Cadence or equivalent EDA digital front end tools
- Strong team orientation, version control, and code documentation habits
- Experience in low power digital ASIC design practices
- Deep knowledge of IC design flow
Additional Requirements
- Must be currently authorized to work in the United States without the need for sponsorship for a non-immigrant visa
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