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Ciena Communications1 week ago

Senior Digital ASIC Design Engineer

On-site · Ottawa, Ontario, Canada

Type
Full Time
Level
Senior Level
Education
Bachelors Degree
Company size
Enterprise

Job Summary

Senior Digital ASIC Design Engineer needed to contribute to top-level ASIC design and integration for WaveLogic products. Responsibilities include interpreting architecture and functional specs, developing and assembling top-level RTL designs integrating multiple IP blocks, maintaining technology-specific libraries, owning tool flows for ASIC top-level integration, creating timing constraints and analyzing synthesis, timing, layout, and backend reports, and lab validation of ASIC prototypes and production silicon. Requires a Bachelor’s degree in Electrical/Computer Engineering or Computer Science, 5+ years in ASIC design, proficiency in Verilog/SystemVerilog/Python, and experience with synthesis and STA; strong communication in English. Nice-to-haves include C/C++/SystemC and ASIC verification experience.

Required Qualifications

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science
  • 5+ years of experience in ASIC design
  • Proficiency with Verilog, SystemVerilog, and Python in digital design workflows
  • Experience with synthesis, static timing analysis (STA), timing closure, and asynchronous clock domain crossing
  • Ability to interpret architecture and functional specifications and collaborate with systems engineers
  • Strong written and verbal English communication in technical environments
  • Nice-to-haves: exposure to C/C++/SystemC; experience with ASIC verification
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Ciena Communications

Senior Digital ASIC Design Engineer

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