Senior DFX Power Methodology Engineer
$196,000–$368,000 year
On-site · Santa Clara, California, United States
Job Summary
Senior DFX Power Methodology Engineer to advance Design-for-X methodologies in power, thermal, and voltage-noise areas for NVIDIA’s manufacturing tests of datacenter GPUs. You will collaborate with Power Architecture and Product Development teams to implement brand-new methodologies for low-power and thermal solutions, perform post-silicon data analysis for power, and deploy DFT methodologies for next-generation products using Applied ML & Gen AI. Mentoring junior engineers on test designs and trade-offs (cost vs. quality) is included. Base salary ranges: 196,000 USD–310,500 USD (Level 5) and 232,000 USD–368,000 USD (Level 6), with equity and benefits; Applications accepted through June 6, 2026. The role requires advanced degrees in electrical/electronic engineering and substantial experience in DFT, power, thermal, and AI-enabled EDA approaches. NVIDIA emphasizes inclusive hiring and equal opportunity employment.
Required Qualifications
- BSEE (or equivalent experience) with 12+ years of experience in DFT design & power
- MSEE with 10+ years of experience in DFT design & power
- PhD with 6+ years of experience in DFT design & power
- Understanding of fundamental DFT topics and VLSI areas of power, timing & voltage noise
- Experience in Power Analysis, Thermal Analysis & IR Drop tools is a plus
- Experience in application of AI for EDA-related problem-solving is a plus
- Excellent knowledge in using statistical tools for data analysis & insights
- Good exposure to multi-functional areas including RTL & clocks design, STA, place-n-route and power
- Experience in Silicon debug and bring-up on the ATE or SLT platforms
- Be able to think like a programmer so that this can be translated into action using AI Coding harnesses
- Outstanding written and oral communication skills with the curiosity to work on rare challenges
- Ways to stand out from the crowd: Experience in managing DFT Power Methodology for designs, Post-silicon debug for thermal & IR Drop, Strong collaboration and interpersonal skills
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