Senior DFT Engineer

Develop and implement DFT architecture including scan insertion, compression, and hierarchical DFT for advanced SoC designs. Generate and optimize ATPG patterns for various fault models, perform failure diagnosis, and design MBIST controllers with repair mechanisms. Implement Boundary Scan, JTAG, and IJTAG infrastructure while executing pre-silicon simulations and Gate-Level Simulation. Support silicon bring-up, ATE pattern validation, and post-silicon debug through close collaboration with RTL, Verification, and Physical Design teams. Analyze coverage metrics to improve test quality and optimize for test time and power.