Senior Design Verification Engineer
On-sitePune, Maharashtra, India
Job Summary
Architect and build novel, scratch-built testbenches for SoC-level verification of GPNPU-based SoCs. Collaborate cross-functionally with architects, HW designers, and SW teams to document comprehensive verification test plans. Implement scalable testbenches using commercial Verification IP (VIP) and/or internal software utilities. Develop directed and random drivers, as well as assembly or C++ programs, to efficiently stress-test SoC subsystems and integration. Verify complex SoC subsystems, including 3rd-party IP (e.g., NoC, PCIe/UCIe, DDR). Leverage VCS and Verilog/C Co-Simulation environments alongside assembly programming and Python scripting to execute test suites. Track, analyze, and communicate verification progress across teams using functional and code coverage metrics. Build out and deploy a fully functional, scratch-built SoC-level UVM verification environment within the first 6–12 months. Achieve target coverage metrics across all critical SoC subsystems and 3rd-party IP blocks. Establish robust co-simulation pipelines that validate HW/SW execution before tapeout.
Required Qualifications
- Minimum 5+ years of dedicated design verification experience on complex SoC/ASIC designs
- Deep expertise in UVM methodology and leading SoC-level verification practices
- Proficiency in SystemVerilog or Verilog, assembly programming, and scripting languages like Python
- Hands-on experience verifying SoC subsystems and 3rd-party IP (e.g., NoC, PCIe/UCIe, DDR)
- Strong computer architecture background with experience in VCS and Verilog/C Co-Simulation
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