Senior Design Verification Engineer
$168,000–$336,000 year
On-site · San Jose, California, United States
Job Summary
Senior Design Verification Engineer to develop a verification environment using GenAI-enabled workflows, leveraging UVM SystemVerilog to drive schedule left-shift and verification efficiency. Role emphasizes building and executing test plans, achieving coverage closure, and collaborating across cross-geographical teams with expertise in ASIC/SoC verification, CPU emulation, and advanced verification methodologies. Strong emphasis on SystemVerilog, SystemC/C++, scripting, and experience with ASIC simulation tools. Attractive salary with benefits and equity; location required in San Jose, CA (US).
Required Qualifications
- 5+ years of Design Verification experience using UVM System Verilog methodology
- Bachelor's degree in Electrical Engineering or Computer Science related majors
- Hands-on experience with GenAI, including development of agentic MCP and skill-based tools
- Strong and relevant expertise with ASIC simulation tools and sophisticated verification methods
- System Verilog, System C or C++, scripting skills
- Experience in SoC plus CPU emulation verification environment
- Proven track record of building test plans and coverage closure
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