Senior Design Verification Engineer
Hybrid · Zürich, Zurich, Switzerland or Cambridge, England, United Kingdom
Job Summary
Senior Design Verification Engineer responsible for applying industrial-strength verification to high-quality open source code bases, including OpenTitan. Roles include designing, implementing, and debugging block- and system-level tests and testbenches using SystemVerilog and UVM; developing test and coverage plans; reviewing contributions to open source projects; triaging nightly regressions; contributing to CI/test infrastructure; and collaborating with partners to convert specifications into verification collateral that enables tapeouts. Candidates should have extensive SystemVerilog/UVM experience, ability to manage verification activities across multidisciplinary teams, proficiency in C/Python for tests, and an undergraduate technical degree. Hybrid working is open to discussion after probation.
Required Qualifications
- 5+ years of industry experience in design verification including substantial SystemVerilog and UVM usage
- Experience across the full verification cycle from initial planning to final tape-out
- Ability to provide work estimates and coordinate work with a project manager
- Comfortable working with engineers across multiple organizations in multidisciplinary teams
- Familiarity with Git and code review using services such as GitHub
- Programming in C and/or Python in tests and automation
- Undergraduate degree in a technical discipline or equivalent experience
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