Senior Design Verification Engineer
$164,470–$311,890 year
Hybrid · Santa Clara, California, United States
Job Summary
Senior Design Verification Engineer responsible for end-to-end verification of chassis and interconnect IP blocks from planning through signoff. Own verification planning and execution, build scalable verification environments with reusable test benches, collaborate across architecture/design/software, drive multiple verification components to functional signoffs, and guide convergence of simulation and formal verification with ML-driven workflows. Requires strong DV/verification depth, proficiency in SystemVerilog/UVM, C/C++, Python, and experience with IPs, memory subsystems, and standard bus protocols; role involves mentoring engineers and enabling high-quality silicon deliveries in a hybrid work model.
Required Qualifications
- Bachelor of Science Degree in Electrical or Computer Engineering, Computer Science, or in a STEM related field
- 10+ years of experience in design verification (DV) with extensive background in IP DV, and subsystem and SoC-level verification
- Experience in interconnects, caches, and memory subsystems, including multiple bus protocols such as AMBA (CHI, ACE, AXI), PCIe, UCIe, and CXL; cache coherency and memory consistency models
- Experience in verification of global functions including debug, trace, clock and power management, RAS, QoS, and security feature
- Experience in simulation and formal verification methodologies including UVM, SVA, ABV, and co-simulation; proficiency in low-power verification techniques, HDL/verification languages, and industry-standard EDA tools
- Hands-on coding experience across SystemVerilog/UVM, C/C++, Python, and build systems
- Experience working with RTL, physical design, and CAD tool flows; contribute outside core DV responsibilities as needed.
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