Senior Design Verification Engineer
$153,500–$310,500 year
HybridSunnyvale, California, United States
Job Summary
Develop testbenches, write test plans, debug failures, and contribute to improving verification methodologies for digital designs. Work alongside experienced engineers to verify correctness and functionality, applying academic foundations to real-world challenges in a collaborative, fast-paced environment. This entry-level role is ideal for recent graduates with coursework in digital logic, HDLs like Verilog or VHDL, and basic verification concepts. The position requires a Bachelor's degree in Electrical, Computer, or Computer Engineering, with preferred qualifications including a Master's degree, SystemVerilog/UVM experience, and exposure to EDA tools. Schedule is hybrid, with an average of 2 days per week from an HPE office.
Required Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science from an accredited institution
- Coursework or academic projects in Digital logic design and computer architecture
- Coursework or academic projects in Hardware Description Languages (HDL) such as Verilog or VHDL
- Basic understanding of verification concepts (simulation, assertions, code coverage)
- Familiarity with at least one programming or scripting language (e.g., Python, C, C++, or SystemVerilog)
- Strong analytical and problem-solving skills
- Effective written and verbal communication skills
- Ability to work collaboratively in a team environment
- Work on average 2 days per week from an HPE office
Desired Qualifications
- Master's degree in Electrical Engineering, Computer Engineering, or a related field
- Academic or class projects involving networking protocols (e.g., Ethernet, TCP/IP, USB, PCIe) or communication protocols (e.g., UART, SPI, I2C, AXI, AMBA)
- Hands-on experience with SystemVerilog and UVM (Universal Verification Methodology) through coursework or personal projects
- Exposure to constrained-random verification, functional coverage, and assertion-based verification techniques
- Experience with EDA tools such as Synopsys VCS, Cadence Xcelium, or Mentor Questa
- Familiarity with scripting for automation (e.g., Python, Tcl, Perl, Shell)
- Coursework or project experience in FPGA prototyping and implementation
- Coursework or project experience in SoC (System-on-Chip) design and integration
- Coursework or project experience in Signal processing or embedded systems
- Contributions to open-source hardware projects or participation in relevant competitions (e.g., IEEE, ACM)
- Coursework or project experience involving AI/ML applications such as Gen AI, using AIML chatbot as a programming aid, etc.
- Internship or co-op experience in a design verification or related role
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