Senior Design for Test (DFT) Engineer
On-site · Limerick, Munster, Ireland
Job Summary
Senior DFT Engineer role focused on specification, architecture, and implementation of DFT across product lines. Responsibilities include delivering high-coverage, low-power, low-test-time ATPG patterns; conducting pre/post-silicon verification and debug; providing silicon test bring-up support and failure analysis; and mentoring junior team members. Requires hands-on Tessent DFT tooling and deep expertise in Scan, Test Compression, At-Speed Test, MBIST, and LBIST, plus scripting in Perl/Python/Tcl. Collaborative, cross-organizational work style and strong communication skills are essential.
Required Qualifications
- 6 - 8 years of directly related experience in ASIC/SoC DFT
- Expert level knowledge of DFT architecture and planning
- Hands on Tessent DFT Tool experience
- Expert level knowledge of Scan, Test Compression, At-Speed Test, MBIST, LBIST
- Hands-on experience of Scan Insertion, Compression Insertion, On-Chip Clock Control Insertion, ATPG, DFT Verification
- Gate-level simulation with SDF
- Silicon test bring up support, failure analysis debug/diagnosis
- Scripting: Perl/Python/Tcl
- Team-player: ability to forge and maintain relationships with peer-organizations
- Strong written and verbal communication skills
- Preferred Qualifications: Experience with Cadence and Synopsys DFT tools
- Experience with IEEE 1149 and JTAG
- Experience with Static Timing Analysis
- Experience with Built-In Self-Test (BIST)
- Experience with Synthesis and DFT Insertion
- Experience with Low Power Scan and UPF
- Export control considerations for sensitive data
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