Senior Design Engineer
HybridSouthampton, England, United Kingdom
Job Summary
Translate algorithm and system architecture requirements into RTL micro-architectures for FPGA and ASIC implementations. Create testbenches, deploy designs onto development platforms for validation, and optimize timing, hardware resources, and power management for high-throughput signal processing. Collaborate across micro-architecture, design, verification, and physical implementation teams to deliver standalone IP and integrated solutions while adhering to engineering methodology and offering design flow improvements. Maintain technical documentation including design specifications and verification plans. AccelerComm develops baseband signal processing technology for 5G satellite base stations, enabling global mobile coverage through hardware-accelerated error resilience and power efficiency.
Required Qualifications
- Expert knowledge of an RTL language (Verilog, SystemVerilog) for complex ASIC/FPGA products
- A strong skillset in delivering digital designs in the ASIC and FPGA industry
- Optimisation of timing and hardware resources for high throughput data or signal processing applications
- Experience in power management techniques, synthesis and timing analysis
- Track record in collaborating across teams to produce integrated solutions
- Experience in technical documentation writing – design specifications, user guides, verification plans
- Expert user of EDA tools for simulation and synthesis
Desired Qualifications
- Knowledge of communications signal processing algorithms (such as error correction, equalisation, channel estimation, beamforming)
- Familiarity with the AMBA bus protocols
- Understanding of UVM verification techniques or practical experience using UVM for IP verification
- Experience using C++/SystemC for design modelling and integration
- Experience with high speed interfaces such as PCI-E or JESD
- Knowledge of a scripting language, such as Python
- Knowledge and appreciation of project methodologies across the design lifecycle, including agile and waterfall, requirement capture and traceability
- Experience with AMD FPGAs and the associated design tools or with any EDA's ASIC backend tools
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