Senior Density Fill Development Engineer
$128,880–$245,160 year
HybridPhoenix, Arizona, United States or Austin, Texas, United States
Job Summary
Design and debug Fill components of Process Design Kits (PDKs), providing algorithmic solutions using tools such as Calibre, ICV, and Pegasus to address density deficiencies and ensure manufacturability compliance. Collaborate with process developers, design rule owners, and end users to define requirements, automate workflows, and develop comprehensive test cases to validate software tools. Innovate in EDA tools and methodologies while partnering with cross-functional teams and external vendors to implement new features. Maintain documentation including training materials and user guides to support robust deployment. This role supports Intel's Design Technology Platform (DTP) in driving advanced process technologies and fostering innovation in design automation.
Required Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
- 8+ years of experience
- Master's degree
- 5+ years of experience
- PhD
- 2+ years of experience
- Minimum 5 years of hands-on experience with at least one industry-standard physical verification platform (Calibre, ICV, or Pegasus)
- Experience with methodology development
- Experience with rule deck debugging
- Experience with production deployment
- 3+ years of direct experience developing, maintaining, or debugging physical verification rule decks using SVRF, TVF, PXL, or PVL/PVTCL for DRC, density, or fill verification applications
- Solid understanding of semiconductor device physics
- Solid understanding of process technology
- Solid understanding of design rules
- Experience in developing algorithmic solutions for physical design challenges in advanced manufacturing nodes
- Strong knowledge of Unix/Linux platforms
- Strong knowledge of computing environments
- Shift 1 (United States of America)
- Primary Location: US, Oregon, Hillsboro
- Additional Locations: US, Arizona, Phoenix, US, California, Santa Clara, US, Texas, Austin
- Hybrid work model
Desired Qualifications
- 5+ years of hands-on experience developing, deploying, or supporting density fill methodologies for semiconductor technologies at 16nm and below
- Experience with ownership of fill rule implementation
- Experience with density compliance
- Experience with manufacturability optimization
- Experience with advanced physical verification techniques, including DRC, and density/fill modules
- Industry experience with other foundry technologies in this domain
- Familiarity with custom layout tools such as Cadence Virtuoso or Synopsys Custom Designer
- Deep understanding of technology scaling challenges and their impact on physical design rules
- Proven track record of collaborating across multiple internal and external teams to deliver optimal solutions
- Exceptional analytical and problem-solving skills with the ability to address cross-disciplinary challenges
- Strong written and verbal communication skills, with the ability to present complex technical concepts clearly
- Leadership experience driving innovation, process improvements, or cross-functional initiatives
- Experience from semiconductor foundries
- Experience from advanced packaging organizations (OSATs)
- Experience from integrated device manufacturers (IDMs)
- Experience from EDA vendors
- Experience contributing to physical verification
- Experience contributing to density-fill methodology development
- Experience contributing to process design kits (PDKs)
- Experience contributing to manufacturing-driven design solutions
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