Senior ASIC Verification Engineer - PMU
On-siteShanghai, Shanghai, China
Job Summary
Collaborate with production SW and power architecture teams to define micro-architecture for power features and implement designs to RTL. Support silicon debug by analyzing how PMU function impacts the system while working with software on the RISC-V core to determine optimal operating points. Requires BS/MS in electrical or computer engineering with 3+ years of experience, including frontend ASIC design and active/low power expertise. Strong communication skills in oral English are essential for frequent interaction with external teams in the USA and India. This role supports NVIDIA's next-generation PMU for AI datacenters, leveraging 17 years of IP development to optimize chip performance and efficiency across idle and active scenarios.
Required Qualifications
- BS / MS in electrical / computer engineering
- 3+ years working experience
- Strong communication skills
- proficient oral English
- Familiar with frontend ASIC design
Desired Qualifications
- MS or equivalent experience
- Experience on active power/low power design
- Play similar role in other system-level control features
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