Senior ASIC verification engineer
$153,500–$310,500 year
On-site · Roseville, California, United States
Job Summary
Senior ASIC verification engineer role focused on designing, analyzing, developing, modifying and evaluating VLSI components and hardware systems. Responsible for architecture and logic design, design verification through software for component and system simulation, and building physical implementations for complex ICs. Leads project teams of Electronic and VLSI engineers and partners, reviews designs for compliance with VLSI guidelines, provides technical leadership, mentoring, and drives innovation and integration of new technologies in the design organization. Onsite role primarily at an HPE office in Roseville, CA, with a salary range of $153,500–$310,500 (U.S. California). Includes opportunities for professional development, inclusion, and a strong emphasis on collaboration across cross-functional initiatives.
Required Qualifications
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering or equivalent
- 10+ years of experience in VLSI design, verification, or implementation
- Experience with Verilog/SystemVerilog
- Experience with scripting languages (Python, PERL, TCL or equivalent)
- Experience with software programming languages (C; C++)
- Experience with UVM methodologies
- Specman knowledge is a plus
- Knowledge and Skills: expert level in electrical engineering fundamentals, VLSI principles, digital logic, and computer architecture
- Proficiency with hardware description languages, EDA tools and FPGA tools
- Strong written and verbal communication skills in English
- Patents/publications in VLSI or hardware components (advantage)
- Ability to lead project teams and mentor staff
- Bachelor/Master level coursework in VLSI design or concepts
- Experience in executive communication and cross-functional collaboration
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