Senior ASIC Verification Engineer
On-site · Hyderabad, Telangana, India
Job Summary
Senior ASIC Verification Engineer role focusing on RTL and subsystem verification for ARM-based SoCs using UVM, Portable Stimulus, and Formal verification flows. Responsibilities include project leadership in test-plan definition, micro-architecture and RTL verification, top-level and block-level functional and performance verification, system use-case verification, and supporting test program development through chip life to production maturity. Collaboration spans firmware, software, DV, FPGA, DFT, SoC integration, and backend teams. Required to have 8+ years of UVM verification experience and proficiency with C/Assembly/SystemVerilog; experience with AMBA AXI/AHB/APB protocols and various interfaces (PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART); scripting skills (Perl, Python, Shell); and familiarity with repository/bug-tracking tools (Bitbucket/Jenkins, JIRA). BE/BTECH or ME/MTECH in EE/EECS/CS or equivalent.
Required Qualifications
- 8+ years of experience in UVM verification and UVM environment development
- Proficiency in test plan definition and testcase development in C/Assembly/SystemVerilog
- Experience with RTL and gate-level verification
- Knowledge of AXI, AHB, APB protocols; experience with PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART interfaces
- Fluency with scripting languages (Perl, Python, Shell)
- Experience with Bitbucket/Jenkins and JIRA
- BE/BTECH or ME/MTECH in EE/EECS/CS or equivalent
- Ability to collaborate with firmware/software/DFT/SoC teams
Additional Requirements
- equal opportunity employer
- visa sponsorship not specified
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