Senior ASIC Timing Engineer

Job Summary

Required Qualifications

• BS (or equivalent experience) in Electrical or Computer Engineering with 8 years experience or MS with 4+ years experience in Synthesis and Timing
• Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and timing convergence
• Expertise in analysis and fixing of timing paths through ECOs including crosstalk and noise analysis
• Expertise in physical design and optimization e.g., placement, routing, cell sizing, buffering, logic restructuring, etc. to improve timing and power, along with a background in implementing them through ECOs
• Background in logic synthesis and/or logical equivalence checking (LEC)
• Expertise and in-depth knowledge of industry standard EDA tools (Synopsys PrimeTime or Cadence Tempus)
• Proficiency in Python, Tcl and Make for automation and scripting tasks

Desired Qualifications

• Background in domain specific STA and timing convergence, such as CPUs, GPUs or Network processor implementation or SOCs
• Understanding of DFT logic and experience with DFT timing closure for various modes e.g., scan shift and capture, transition faults, BIST, etc.
• Knowledge of deep sub-micron technology and associated process variations effects, including modeling and converging considering process variations
• Experience in methodology and/or flow development as well as automation