Senior ASIC Physical Design Technical Lead

Senior ASIC Physical Design Technical Lead responsible for fullchip floorplanning and RTL-to-GDSII implementation, including clock planning, power grid, pin assignment, and hierarchy-driven placement. Leads handson efforts in floorplan, power optimization, and timing/power/performance goals; collaborates with RTL, DFT, EDA vendors, and tool/flow teams to enable best-in-class design methodologies. Requires proficiency in UPF low-power methodologies and experience with signoff workflows involving foundries and standard cell IP vendors. Strong emphasis on using tools like Innovus, Tempus/Primetime, Redhawk/Voltus, and Calibre for P&R, DRC/P,Z, and CTS; Python scripting and AI-assisted productivity are valued. Salary ranges are disclosed for U.S./Canada locations; compensation depends on location, skill, and experience.