Senior ASIC Physical Design Engineer - San Jose, CA (100% Onsite) - FTE Permanent role - AS
On-siteSan Jose, California, United States
San Jose, California, United StatesOn-siteFull TimeSenior LevelBachelors Degree
Full TimeSenior LevelBachelors Degree
Job Summary
Execute Physical Design, Physical Verification, and Timing Closure for next-generation AI designs, including top-level STA, EM/IR analysis, Place and Route, Clock Tree Synthesis, and Floor-planning. Develop Flow and Methodology while collaborating with IC Design RTL Engineers to drive Netlist to silicon tape-out. Requires 8+ years of experience, Bachelor's in Electrical Engineering, and proficiency in TCL/PERL scripting and EDA tools. This role is 100% onsite in San Jose, CA, five days a week.
Required Qualifications
- 100% Onsite
- 5-days a week
- FTE Permanent role
- in-depth knowledge and expertise in Physical Design aspects of taking Netlist to silicon tape-out
- Execution of Physical Design, Physical Verification, and Timing Closure
- Timing closure through various methods and strategies; preferable in-depth experience in top-level STA
- EM/IR Analysis, Place and Route
- Clock Tree Synthesis; experience with custom clock trees, insertion reduction and skew balancing techniques
- Floor-planning and Layout; preferable in-depth experience in top-level floorplanning
- Flow and Methodology Development
- Collaborating with IC Design RTL Engineers
- TCL/PERL Scripting
- Proficiency in related EDA Tools
- Full physical design cycle experience: RTL to Tape-out
- Excellent verbal and written communication skills
- Bachelor's degree required in Electrical Engineering or Electronics Engineering
- 8+ Years of relevant experience
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