Senior ASIC Physical Design Engineer, Netlisting
$136,000–$218,500 year
HybridAustin, Texas, United States or Santa Clara, California, United States
Job Summary
Drive physical design of high-frequency and low-power CPUs, GPUs, and SoCs at block, cluster, and full-chip levels, focusing on netlist-related aspects such as equivalence checking, asynchronous checking, clock domain crossing checks, and MTBF analysis. Manage timing convergence, generate and manage timing constraints, and handle ECO generation and implementation. Assist with logic synthesis, netlist quality checks, and full-chip Static Timing Analysis using industry-standard EDA tools. Apply scripting languages like Python and TCL to improve workflows and productivity. This role supports NVIDIA's AI infrastructure and deep learning initiatives, contributing to the next era of computing through autonomous problem-solving and advanced hardware architecture expertise.
Required Qualifications
- BS (or equivalent experience) in Electrical or Computer Engineering
- 5+ years' experience
- MS (or equivalent experience)
- 3+ years' experience
- Expertise in logic equivalence checking/FV from RTL to tapeout with industry-standard tools
- Deep understanding of hardware architecture
- Hands-on skills in RTL/logic design for timing closure
- Experience in clock-domain-crossing checking
- MTBF analysis
- Background with logic synthesis at either block or full-chip level
- Background with logic synthesis at project execution and/or flow development
- Strong experience in full-chip/sub-chip Static Timing Analysis (STA)
- Timing constraints generation and management
- Timing convergence
- Expertise and in-depth knowledge of industry standard EDA tools in related fields
- Proficiency in programming and scripting languages, such as, Perl, TCL, Make, Python, etc.
Desired Qualifications
- Experience in logic synthesis and equivalence checking/FV
- Familiarity with industry tools and flow
- Strong hands-on debugging capability and problem-solving skills
- Background in DFT timing closure for various modes e.g. scan shift and capture, transition faults, BIST, etc.
- Experience or a strong drive to improve workflows and productivity through effective AI utilization
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