Senior ASIC DV Engineer

Senior ASIC DV Engineer responsible for development and verification of complex SOCs targeting Touch Controller and Wireless Charging initiatives. Architect block- and full-chip verification environments using HVLs (UVM) and constrained random techniques for SOCs with embedded CPUs and mixed-signal interfaces. Leverage mixed-signal simulations (AMS, Spice) to develop test plans and coverage metrics, write block- and chip-level tests, debug RTL and gate simulations, and collaborate with design engineers to verify fixes. Produce diagnostics for FPGA prototype validation and ASIC pre-tapeout, replicate silicon bugs in simulation, convert verification tests to test patterns, assist Test Engineers with ATE vector bring-up, and evaluate/implement new verification methodologies and automation scripts. Experience with low-power silicon verification (UPF flow) and translating customer requirements into full-chip verification plans is required. Compensation includes base salary range $141,300–$226,000, discretionary bonus, and equity; Broadcom offers comprehensive benefits and equal opportunity employment.