Senior Analog/RF Layout Engineer
HybridBengaluru, Karnataka, India
Job Summary
Drive layout and physical implementation of analog/mixed-signal circuits, high-speed interfaces (SerDes, PAM4), and supporting digital blocks. Own block-level floorplanning, placement, routing, and integration for complex mixed-signal ICs, translating schematics into optimized layouts tuned for matching, parasitics, signal/power integrity, and manufacturability. Ensure compliance with foundry rules (DRC, LVS, ERC) and support top-level assembly across analog, digital, and high-speed domains. Review post-layout extraction, apply symmetry and shielding best practices, and partner with packaging teams on bump planning and ESD structures. Drive layout-related issues affecting yield or production readiness, contribute to tapeout signoff, and mentor junior engineers. Requires 6–8 years of custom IC layout experience with strong Cadence Virtuoso command.
Required Qualifications
- Bachelor's in Electrical Engineering or related
- 6–8 years in custom IC layout for analog, mixed-signal, and high-speed designs
- Strong hands-on command of the Cadence Virtuoso custom-design platform
- Working expertise across the following (or close equivalents): Virtuoso Layout Suite (XL / GXL) for connectivity- and constraint-driven custom layout, including Modgen and structured/array generation for matched devices
- EM simulators like EMX, HFSS, Lorentz Peakview, etc.
- Virtuoso Electrically Aware Design (EAD) for in-design EM/IR and parasitic-aware high-speed layout
- Quantus QRC extraction
- Physical verification with Cadence Pegasus (or Assura) and/or Siemens Calibre — DRC, LVS, ERC, density
- Voltus-Fi / Virtuoso Power for EM/IR signoff
- SKILL scripting plus Python / Perl / TCL for automation
- Strong foundation in matching, symmetry, shielding, parasitic control, thermal management, and signal integrity
- Command of device-level techniques (common-centroid, interdigitation, guard rings, isolation structures)
- Solid grasp of DRC, LVS, ERC, parasitic extraction, EM/IR analysis, and physical signoff flows
- Comfortable working in Linux
- Minimum Qualifications: Bachelor's or Master's in Electrical Engineering or equivalent field
- 3+ years of layout design experience in analog, mixed-signal, or high-speed IC development
- Hands-on experience taking block-level layout through tapeout
- Strong custom-layout, physical-verification, and parasitic-aware implementation skills with Cadence Virtuoso or comparable tools
Desired Qualifications
- Master's a plus
- Interest in growing into layout leadership
- Familiarity with ASIC/SoC tapeout processes and layout automation scripting
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