RTL Power Optimization Engineer – New College Grad 2026
$116,000–$189,750 year
On-siteSanta Clara, California, United States
Job Summary
Use internally developed tools and industry standard pre-silicon gate-level and RTL power analysis tools to improve product power efficiency for NVIDIA's next-generation GPUs and networking chips. Apply artificial intelligence to deliver RTL and architecture power optimization solutions, then develop best practices for pre-silicon analysis. Perform comparative power analysis to spot trends and anomalies, interacting with architects and RTL designers to interpret data, identify power bugs, and drive implementation fixes. Select and run diverse workloads for analysis, prototype new architectural features in Verilog, and analyze power impacts. This role targets new college graduates pursuing or recently completing a MS or PhD in Electrical or Computer Engineering with coursework in AI, Digital Design, and VLSI.
Required Qualifications
- Pursuing or recently completed a MS or PhD in Electrical Engineering, Computer Engineering, or related fields
- Understanding of RTL power optimization fundamentals, including switching activity, clock/enable efficiency, and common low‐power design patterns at the RTL level
- Knowledge of backend flows such as logic synthesis and place‐and‐route, and how RTL decisions impact post‐layout power and timing
- Familiarity with RTL implementation of low‐power techniques (e.g., clock gating, operand isolation, power gating strategies, multi‐VT usage) and their trade‐offs
- Exposure to industry power analysis tools such as PowerArtist, PrimeTime PX, or equivalent, including running power analysis and interpreting reports to guide design changes
- Strong Python programming skills for building automation scripts, data pipelines, and AI/ML‐driven analysis flows for RTL power optimization
- Coursework and/or hands‐on experience in Machine Learning and Artificial Intelligence, with ability to apply ML techniques to EDA and silicon power problems
- Previous experience debugging RTL or gate‐level power anomalies by tracing logic cones, examining activity/toggle data, and identifying root‐cause structures or scenarios
- Strong written and verbal communication skills to document methodologies, present power findings, and explain AI/ML‐based insights to both design and tools teams
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