RTL Design Engineer
On-siteSingapore, Singapore or Central, Louisiana, United States
Singapore, Singapore or Central, Louisiana, United StatesOn-siteFull TimeSmall
Full TimeSmall
Job Summary
Perform RTL design of IP using Verilog/SystemVerilog, conducting design verification, formal verification, and code coverage analysis. Understand timing constraints to ensure the IP passes post-layout simulation and create clear, precise documentation for the design. Support the post-silicon validation effort. This role is part of a team focused on digital IP development.
Required Qualifications
- Understanding design specification and performing RTL design of the IP using Verilog/System Verilog
- Perform design verification, formal verification and code coverage analysis of the IP
- Understanding timing constraints and applying right timing constrints
- Create clear and precise documentation for the design
- Support post-silicon validation effort
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