RTL Design Engineer (Silicon Engineering)
$125,000–$175,000 year
On-site · Irvine, California, United States or Redmond, Washington, United States
Job Summary
RTL DESIGN ENGINEER (SILICON ENGINEERING) at SpaceX responsible for designing ASICs/FPGA-based IP for Starlink, participating in full design lifecycle from architectural discussions to validation, and collaborating with cross-functional teams to deliver advanced digital/communication datapaths. Key duties include implementing IP for complex SoCs in Verilog/SystemVerilog, high-level architectural design, lab bring-up and validation, and ensuring integration with backend/implementation teams. Required to have a Bachelor's in a relevant engineering/physics field and 1+ years of RTL design experience; preferred Master’s in Electrical/Computer Engineering and experience with DSP blocks, AXI/AHB/APB protocols, HDL simulators, and Python scripting. Candidates should be able to work extended hours or weekends as needed and thrive in a dynamic, cross-functional environment. ITAR-compliant eligibility is specified for employment. Compensation offers ranges for ASIC Design Engineer levels I and II, with comprehensive benefits and relocation policy as part of total rewards.
Required Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or Physics
- 1+ years of experience in RTL Design using SystemVerilog, Verilog or VHDL
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