RTL Design Engineer
HybridMarkham, Ontario, Canada
Job Summary
Develop and maintain block level RTL IP and MP subsystems' feature spec, micro-architecture, and synthesizable RTL design methodology. Debug RTL designs using C-DPI directed test methodology and achieve design feature closure by triaging regressions and resolving technical issues with design, verification, and other teams. Participate in verification testbench specification and influence architecture development while debugging integration issues with SoC teams. Provide technical leadership in IP functionality and design methodology development for embedded micro-processor subsystems vital to AMD's security, cryptography, and high-throughput DMA applications.
Required Qualifications
- Proven understanding of CPU and MP subsystem architecture
- Proven understanding of datapath accelerator RTL microarchitecture
- Proven experience with FPGA based emulation and prototyping methodology
- Proficient in Verilog
- Proficient in System Verilog
- Excellent knowledge about state-of-art RTL design and verification methodology and best practices
- Excellent knowledge about C-DPI test design
- Excellent understanding of standard bus/interface protocols (i.e. AXI, AHB, AMBA)
- Proven experience with ASIC design tools: synthesis, linting, simulation, debugging, power aware simulation, etc.
- Relevant design domain specific knowledge
- Technical leadership capability
- Bachelor's Degree or Master's Degree in Electrical Engineering, Computer Engineering, or Computer Science, or possibly a related field
Desired Qualifications
- Master's Degree preferred
- Proficient in Tcl
- Proficient in Ruby
- Proficient in Perl
- Proficient in Python
- Proficient in Makefile
- Proficient in System Verilog (an extra asset)
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