RTL Design Engineer
HybridMarkham, Ontario, Canada
Job Summary
Design and deliver high-quality PCIe subsystem RTL, translating architecture requirements into robust, reusable digital blocks. Develop and maintain RTL for complex IP, author coding guidelines, and drive design reviews to resolve debug and correctness issues. Ensure RTL closes cleanly through front-end signoff including Lint, CDC/RDC, synthesis, LEC, and STA while collaborating with verification, physical design, and architecture teams for seamless handoff. Support subsystem integration and SoC delivery to achieve first-pass silicon success. Work within the PCIe IP Enablement team to mentor engineers and set design development direction.
Required Qualifications
- RTL design experience
- Proven end-to-end ownership of complex digital IP/subsystems from architecture through tape-out
- High accuracy
- Detail-oriented
- Strong communication skills
- Strong problem-solving skills
- Ability to help set design development direction
- Ability to mentor other engineers on the team
- Micro-architecture and RTL design for PCIe subsystem blocks
- Ability to develop and maintain RTL for complex digital blocks
- Ability to author and enforce RTL coding guidelines and design documentation
- Ability to translate architecture requirements into robust, reusable, high-quality RTL
- Ability to drive design reviews
- Ability to resolve complex RTL debug and correctness issues
- Ability to support subsystem integration and SoC delivery
- Ability to ensure RTL closes cleanly through front-end signoff — Lint, CDC/RDC, synthesis, LEC, STA
- Ability to collaborate with verification, physical design, and architecture teams for seamless design handoff and sign-off
- Bachelor's or Master's degree in Electrical Engineering / Computer Engineering
Desired Qualifications
- Strong RTL design and micro-architecture experience on complex digital IP/subsystems, from RTL to tape-out
- Strong AI knowledge and experience in it's usage to develop skills and agents
- Direct PCIe protocol and subsystem design experience
- Proficiency with RTL quality flows: Lint, CDC/RDC, synthesis, LEC, and STA
- Experience with Verilog / SystemVerilog RTL design, VCS simulation, and Perl/Shell scripting
- Familiarity with subsystem integration (tile flow, repeaters, SRAM generation, ECO) and DFx awareness (DFT / DFD)
- Excellent problem-solving and debugging skills
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